Crdom: Cell Re-ordering Based Domino On-the-fly Mapping

This Domino logic is often the choice for designing high speed CMOS circuits. Often VLSI designers choose library based approaches to perform technology mapping of large scale circuits involving static CMOS logic style. Cells designed using Domino logic style have the flexibility to accommodate wide range of functions in them. Hence, there is a scope to adopt a library free synthesis approach for circuits designed using Domino logic. In this work, we present an approach for mapping a domino logic circuit using an On-the-fly technique. First, we present a node mapping algorithm which maps a given Domino logic netlist using On-the-fly technique. Next, using an Equivalence Table, we re-order the cells along the critical path for delay, area benefit. Finally, we find an optimum re-ordering set which can obtain maximum delay savings for a minimum area penalty. We have tested the efficacy of our approach with a set of standard benchmark circuits. Our proposed mapping approach (CRDOM) obtained 21% improvement in area and 17% improvement in delay compared to existing work.